Sub-Terahertz/Terahertz Silicon Transceivers for Chip-to-Chip Short-Range Wireless Interconnects

One of the major bottleneck in computing systems (high-performance, personal computers, or handheld smart devices), is ever-increasing requirement of broadband wireline data transmission and reception between CPU, GPU, memory and other peripheral chips and/or boards. Wireline interconnect poses several problems including cross-talk between signals that degrades the signal quality, increased delay/latency, increased power consumption etc.
One possible solution is to embed wireless transceivers within these chips instead of wireline connections. For this purpose, sub-terahertz (>100GHz, can also be called as sub-millimeter-wave) and terahertz (=>300GHz) frequency ranges are pronounced extensively owing to much smaller wavelengths compared to common wireless communication frequencies. As a result, on-chip antennas can be integrated with transceivers and decreases system integration complexity with a very small silicon area overhead (hence less cost).
Within this project, we will clearly define the problems for different chip-to-chip or even board-to-board scenarios; define the requirements for chip-to-chip wireless interconnects, e.g. data-rate, wireless communication distance, latency etc., for different application scenarios; and conceptually design/calculate/simulate sub-terahertz/terahertz chip-to-chip wireless transceiver systems.